Advances in Computer Systems Architecture: 8th Asia-Pacific by Tetsuya Sato, Hitoshi Murai (auth.), Amos Omondi, Stanislav

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By Tetsuya Sato, Hitoshi Murai (auth.), Amos Omondi, Stanislav Sedukhin (eds.)

This convention marked the ?rst time that the Asia-Paci?c desktops structure convention was once held outdoor Australasia (i. e. Australia and New Zealand), and was once, we are hoping, the beginning of what's going to be a typical occasion. The convention begun in 1992 as a workshop for computing device architects in Australia and accordingly constructed right into a full-?edged convention protecting Austra- sia. extra significant alterations ended in the current convention. The ?rst used to be a metamorphosis from “computer structure” to “computer structures architecture”, a metamorphosis that famous the significance and shut courting to desktop arc- tecture of convinced degrees of software program (e. g. working structures and compilers) and of alternative parts (e. g. computing device networks). the second one switch, which re?ected the expanding variety of papers being submitted from Asia, used to be the substitute of “Australasia” with “Asia-Paci?c”. This year’s occasion was once for that reason fairly signi?cant, in that it marked the start of a really “Asia-Paci?c” convention. it's meant that during the long run the convention venue will exchange among Asia and Australia/New Zealand and, even if nonetheless small, we are hoping that during time the convention will become an enormous one who represents Asia to an analogous - tent as present significant computer-architecture meetings in North the USA and Europe signify these regions.

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Extra resources for Advances in Computer Systems Architecture: 8th Asia-Pacific Conference, ACSAC 2003, Aizu-Wakamatsu, Japan, September 23-26, 2003. Proceedings

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Multi-threaded instruction execution need not suffer from the problems encountered using speculative execution, with one exception and that is fundamental, it is synchronising across many concurrently issued instructions and requires a large register file. In a threaded microprocessor, it is not necessary to issue instructions in a thread out-of-order and hence we need only deal with true data dependencies. This can simplify processor design considerably, see [11], which considers a range of processor designs in developing chip multi-processors, it suggests a packing density difference of a factor of 8 between in-order issue and out-of-order issue processors.

1 0 0 20 40 60 iterations 80 100 120 Fig. 2. Relative performance of micro-threaded (solid lines) vs conventional pipeline (dashed lines) on Livermore K3 loop with 128 registers. 1 0 0 10 20 30 40 50 60 70 80 90 100 Iterations per pipeline Fig. 3. Performance of a micro-threaded CMP of 1, 2 and 16 processors on Livermore K7 loop. 2 Micro-threaded Model Now let us look at the model these results are based on in more detail in order to understand how and why these results are possible. Figure 4 shows a modified pipeline, with shared and duplicated parts indicated by shading.

In 1965, Intel’s founder Gordon Moore predicted that the number of transistors on a chip would double every 2 years. His prediction of exponential growth has not only been achieved but in some cases exceeded. On the other hand, the market is all about inertia or lack of change. At ACAC 2000, the invited speaker Rumi Zahir, who led the team responsible for the instruction set architecture of IA-64, told us an anecdotal story about the briefing his team had been given by Andy Grove. They were given a clean sheet to do whatever they wanted, but with one exception...

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